Re-arrange patch files

Some of the patches are applied to files in subdirectories of ::/Kernel and ::/Adam. The directory tree has been re-arranged in such a way as to allow them to be #included without having the compiler backtrack to their parent directory.

1 files changed, 80 insertions, 0 deletions

diff --git a/Adam/ABlkDev/Patches/Mount2CaseAFDC.HC b/Adam/ABlkDev/Patches/Mount2CaseAFDC.HC
new file mode 100644
index 0000000..2e70791
--- /dev/null
+++ b/Adam/ABlkDev/Patches/Mount2CaseAFDC.HC
@@ -0,0 +1,80 @@
+// PATCH: Add the ability to configure floppy BlkDevs (part 1 of 2)
+// FILE: ::/Adam/ABlkDev/Mount.HC
+// TO INSTALL: #include this file at the end of the first switch statement.
+// ADAM PATCH: Must be installed after kernel patches!
+
+case BDT_FLOPPY:
+  do {
+    "Include $PURPLE$0x$FG$ prefix.\nI/O Port Base:\n";
+    GetS(base0_buf,STR_LEN);
+  } while (!Str2I64(base0_buf))
+  do {
+    "Drv Num:\n";
+    unit=GetChar-'0';
+  } while (0<=unit<=3)
+  "If you have a 3.5-inch high-density (1.44 Meg)\n"
+    "floppy disk, there are some default params you can use.\n"
+    "Otherwise, you will need to set the manually (Intel's datasheet\n"
+    "for the 82077AA is very useful here).\n\n"
+    "Use default params ";
+    If (YorN) {
+      defaults=TRUE;
+    } else {
+      "The folowing parameters are used to configure the ctrlr:\n"
+	"Most can be entered in either decimal or hex, but the head\n"
+	"count, sector size, and data rate take single decimal digits.\n"
+      do {
+	"Cylinders:\n";
+	GetS(cyl_buf,STR_LEN);
+      } while (!Str2I64(cyl_buf));
+      do {
+	"Heads:\n";
+	heads=GetChar-'0';
+      } while (1<=heads<=2);
+      do {
+	"Sectors:\n";
+	GetS(spt_buf,STR_LEN);
+      } while (0<=Str2I64(spt_buf)<=255);
+      do {
+	"Sector Size (128<<X bytes):\n";
+	size=GetChar-'0'
+      } while (0<=size<=7);
+      if (size==0) {
+	do {
+	  "DTL (data length):\n";
+	  GetS(dtl_buf,STR_LEN);
+        } while (1<=Str2I64(dtl_buf)<=128);
+      } else {
+	dtl_buf="0xFF"; // If sect size is not 128, DTL is set to 255
+      }
+      do {
+	"Step Rate:\n";
+	GetS(srt_buf,STR_LEN);
+      } while (0<=Str2I64(srt_buf)<=15);
+      do {
+	"Head Unload Time:\n";
+	GetS(hut_buf,STR_LEN);
+      } while (0<=Str2I64(hut_buf)<=15);
+      do {
+	"Head Load Time:\n";
+	GetS(hlt_buf,STR_LEN);
+      } while (0<=Str2I64(hlt_buf)<=127);
+      do {
+	"GPL1 (normal GAP3 len):\n";
+	GetS(gpl1_buf,STR_LEN);
+      } while (1<=Str2I64(gpl1_buf)<=255);
+      do {
+	"NOTE: Setting GPL2 to 0 will disable low-level fmt!\n";
+	"GPL2 (fmt GAP3 len):\n";
+	GetS(gpl2_buf,STR_LEN);
+      } while (0<=Str2I64(gpl2_buf)<=255);
+      do {
+	"*** Data Rates ***\n"
+	  "0=500 Kbit\n"
+	  "1=300 Kbit\n"
+	  "2=250 Kbit\n"
+	  "3=1 Mbit (Not Supported)\n\n";
+	"Data Rate:\n";
+	bps=GetChar-'0'
+      } while (0<=bps<=3);
+    }
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