From 9105ddf464ee7843bbabcebae41d75be5bd5dd80 Mon Sep 17 00:00:00 2001 From: Harley Travis Date: Sat, 27 Jun 2026 11:57:11 -0500 Subject: Update FDCSelDrv FDCSelDrv was patched to preserve the other DOR bits, and not reset the controller when selecting a drive, which caused I/O timeouts. --- Kernel/BlkDev/DskFDC.HC | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) (limited to 'Kernel/BlkDev/DskFDC.HC') diff --git a/Kernel/BlkDev/DskFDC.HC b/Kernel/BlkDev/DskFDC.HC index 7517469..9587737 100644 --- a/Kernel/BlkDev/DskFDC.HC +++ b/Kernel/BlkDev/DskFDC.HC @@ -183,17 +183,21 @@ U0 FDCMotor(CBlkDev *bd, Bool onoff) U0 FDCSelDrv(CBlkDev *bd) { // Select the drive assigned to this blkdev + U64 dor; // Set the CCR appropriately - OutU8(bd->base0+FDC_CCR_DSR,bd->bps); + OutU8(bd->base0+FDC_CCR_DIR,bd->bps); // Send a "SPECIFY" command FDCSendByte(bd,FDC_SPECIFY); FDCSendByte(bd,bd->srt<<4|bd->hut); // Step Rate Time, Head Unload Time - FDCSendByte(bd,bd->hlt<<1|!bd->dma); // Head Load Time, DMA + FDCSendByte(bd,bd->hlt<<1|0); // Head Load Time, DMA - // Set drv sel in DOR (and enable DMA/IRQs) - OutU8(bd->base0+FDC_DOR,8|bd->unit); + // Set drv sel in DOR + dor=InU8(bd->base0+FDC_DOR); + dor&=~2; // Clear the drive select bits + dor|=bd->unit; + OutU8(bd->base0+FDC_DOR,dor); } Bool FDCInit(CBlkDev *bd) -- cgit v1.2.3